In these years, an improvement for large capacity of memory is now continuously made in a semiconductor device such as DRAM (Dynamic Random Access-Memory) and size of semiconductor chip is also increasing corresponding to such large capacity.
As the technology for loading such large size semiconductor chip, the LOC (Lead On Chip) method has been proposed in which an end part of a lead frame is located, for example, at an upper side of a semiconductor chip.
Meanwhile, the LOC method has proposed, in order to realize large capacity, a semiconductor device introducing the structure in which a couple of semiconductor chips forming DRAM of the same capacity are laminated and these semiconductor chips are sealed by the identical resin sealing material.
This semiconductor device (memory system) has a structure that the semiconductor chips are laminated with the circuit forming surfaces provided opposed with each other and a lead is divided to two branching leads divided to upper and lower leads at an inside of a resin sealing material.
One branching lead among two branching leads is bonded and fixed to a circuit forming surface of one semiconductor chip via an insulating film and is connected to an external terminal of the circuit forming surface via the bonding wire.
Moreover, two branching leads are respectively formed of different members in which one branching lead is guided to an external side of the resin sealing material and is then integrated with an external lead formed in a predetermined shape, while the other lead is joined with the one branching lead at the inside of the resin sealing material and connected electrically and mechanically.
That is, the lead (external terminal) extending at the inside and outside of the resin sealing material is composed of the external lead guided to the external side of the resin sealing material, one branching lead integrated to this external lead and the other branching lead joined with one branching lead.
Such semiconductor device is explained in detail in the Japanese Unexamined Patent Publication No. HEI 7-58281.
Following references have been found by the search for cited reference after completion of the present invention by the inventors thereof.
That is, the Japanese Unexamined Patent Publication No. HEI 9-246465 (corresponding U.S. Pat. No. 5,804,874) discloses a laminated chip package for selecting only one chip from two laminated memory chips with the control signals RAS0 and RAS1.
The Japanese Unexamined Patent Publication No. HEI 7-86526 discloses a package including two memory integrated circuits to avoid collision of I/O signals by setting only one memory integrated circuit to an active condition with a CE terminal.
The Japanese Unexamined Patent Publication No. HEI 4-302165 (corresponding U.S. Pat. No. 5,211,485) discloses a semiconductor memory device in which first and second semiconductor memory elements having the same function are fixed on the front and rear surfaces of a tab, these two memory elements are respectively provided with a means for giving an output impedance control signal and a data input/output operation activating signal and also commonly provided with a means for giving the control signal and data input/output signal power source other than the output impedance control signal and the data input/output operation activating signal.
The Japanese Unexamined Patent Publication No. HEI 3-181163 (corresponding U.S. Pat. No. 5,512,783) discloses a semiconductor chip package including an external case providing, at the inside thereof, one or a plurality of semiconductor chips sealed in the capsule and having four chip selection pins (CS0 to CS3), two write acknowledgment pins (WE0 to WE1) and two output acknowledgment pins (OE0 to OE1).